Scan architectures are commonly used to test digital circuitry in integrated circuits (IC). Typical scan architectures scan in a test pattern, perform an operation with the test pattern and capture the results, then scan out the results while scanning in the next test pattern in an overlapped fashion. In other configurations, scanning may be non-overlapped and share bi-directional data pins.
Testing and debugging of a new application specific integrated circuit (ASIC) or of a new or modified application program running on an ASIC requires insight into the internal workings of busses and program execution. The IEEE 1149.1 (JTAG) standard has proven to be a very robust solution to a variety of test and debug systems, enabling a rich ecosystem of compliant products to evolve across virtually the entire electronics industry; however, increasing chip integration and rising focus on power management has created new challenges that were not considered when the standard was originally developed. The Mobile Industry Processor Interface (MIPI) Test and Debug Working group has selected a new test and debug interface, called P1149.7, which builds upon the IEEE1149.1 standard. P1149.7 enables critical advancements in test and debug functionality while maintaining compatibility with IEEE 1149.1.
Other features of the present embodiments will be apparent from the accompanying drawings and from the detailed description that follows.